5.6 Multiplexer/Demultiplexer

In the realm of digital electronics, multiplexers (Mux) and demultiplexers (Demux) are indispensable combinational logic circuits that play a pivotal role in data routing, communication, and system design. Often referred to as "data selectors" and "data distributors" respectively, these devices enable the efficient management of information flow by allowing multiple data streams to share a single transmission line, or conversely, directing a single data stream to one of several destinations. Their ability to dynamically control data paths makes them fundamental building blocks in various applications, from telecommunications and computer memory systems to complex data acquisition and processing units.

 

Part 5.6.1 Multiplexer

An MSI circuit capable of selecting a single input from several inputs and routing the selected input to a single output. The output line is connected to any of the input line depending on the logic combinations at the select lines. It is also called a data selector.

A diagram of a machine

AI-generated content may be incorrect.

Figure 1. Block Diagram of a Multiplexer

 

Table 1. Function Table of Multiplexers

S1

S0

Y

0

0

I0

0

1

I1

1

0

I2

1

1

I3

 

A diagram of a machine

AI-generated content may be incorrect.

Figure 2. Logic Circuit of 4x1 Multiplexer (from: Nigde University)

 

Part 5.6.1 .1Boolean Function Implementation using multiplexers

Steps:

1.        Express the Boolean function in SOP form.

2.                  For n variables, connect the n-1 variables to the selection lines.

3.                  List the inputs to the multiplexer and under them list the minterms in two rows. The first row is with A complemented and the second row is with A uncomplemented.

4.                  Circle all the minterms of the function and apply the following:

a.) If two minterms in a column are not circled, apply 0 to the corresponding multiplexer input.

b.) If the two minterms are circled, apply 1 to the corresponding multiplexer input.

c.) If the bottom minterm is circled and the top is not, apply A to the corresponding multiplexer input.

d.) If the top minterm is circled and the bottom is not, apply A' to the corresponding multiplexer input.

 

Example no. 1

Implement the following function with a multiplexer.

F(A,B,C,D)=Σ(0,1,3,4,8,9,15)

 

Solution no. 1

Based on the given function which involves four variables, a multiplexer with three selection lines and eight inputs is needed. Applying B, C, and D to the selection lines and A to the minterms, the implementation table is shown as:

 

A table with numbers and circles

AI-generated content may be incorrect.

A diagram of a circuit board

AI-generated content may be incorrect.

 

 

 

Example of a multiplexer IC is the 74x151 8-input, 1-bit multiplexer that comes in a 16-pin dual-in-line package.

 

Example no. 2

 

Implement F(A,B,C,D)=Σ(0,3,5,6,8,9,14,15)

 

Solution no. 2

 

Truth table:

 

A

B

C

D

F

0

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

0

1

1

1

0

1

0

0

0

0

1

0

1

1

0

1

1

0

1

0

1

1

1

0

1

0

0

0

1

1

0

0

1

1

1

0

1

0

0

1

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

0

1

1

1

1

1

1

 

 

Implementation Table:

 

 

I0

I1

I2

I3

I4

I5

I6

I7

A’

0

1

2

3

4

5

6

7

A

8

9

10

11

12

13

14

15

 

1

A

0

A’

0

A’

1

A

 

Schematic Diagram:

 

 

A diagram of a circuit board

AI-generated content may be incorrect.

Part 5.6.2 Demultiplexer

A combinational circuit that receives multiplexed information on a single line and transmits this information on one of 2n possible output line. The selection of a specific output line is controlled by the bit values of n selection lines.

A decoder with an enable input can function as a demultiplexer.

A diagram of a decoder

AI-generated content may be incorrect.

Figure 3. Decoder with enable pin

 

 

A diagram of a computer chip

AI-generated content may be incorrect.

Figure 4. Demultiplexer

 

 

Example IC is 74x155 which is a 2-bit, 4-output demultiplexer

 

E

A

B

D0

D1

D2

D3

1

x

X

1

1

1

1

0

0

0

0

1

1

1

0

0

1

1

0

1

1

0

1

0

1

1

0

1

0

1

1

1

1

1

0

 

A diagram of a circuit

AI-generated content may be incorrect.

Figure 5. Logic Circuit of IC 74x155